1. Field
The application relates to a semiconductor memory which receives a row address signal and a column address signal to operate.
2. Description of the Related Art
A semiconductor memory such as a pseudo SRAM has DRAM memory cells (dynamic memory cells) and operates as an SRAM by internally performing a refresh operation of the memory cells automatically. The pseudo SRAM performs the refresh operation without being recognized by a controller such as CPU during a period in which a read operation or a write operation is not performed. The refresh operation is performed using an address signal generated by an internal address counter in response to an internal refresh request which occurs periodically in the pseudo SRAM (for example, Japanese Laid-open Patent Publication No. H01-125796).
The memory core of a pseudo SRAM has the same structure as the memory core of a DRAM, and the memory core operates as a DRAM. Accordingly, when DRAMs and pseudo SRAMs are manufactured, the test efficiency improves if the same program as that for the DRAMs can be used for testing the pseudo SRAMs. Particularly, a test pattern for writing a predetermined data pattern in memory cells arranged in a matrix form is designed depending on the layout structure of a memory core. Therefore, it is wasteful to design test patterns respectively for pseudo SRAMs and DRAMs having memory cores of the same structure.
However, in a pseudo SRAM, a row address signal and a column address signal are supplied simultaneously via terminals different from each other together with an access command (address non-multiplex type). On the other hand, in a DRAM, a row address signal and a column address signal are supplied sequentially from a common address terminal (address multiplex type). Therefore, conventionally, it has not been possible to use a test pattern for a DRAM to test a pseudo SRAM.